
CDB4228A
DS511DB1 23
REFCLK SELECT
ON
OFF
OSC
REFCLK_CTRL3
SPDIF_MCLK
REFCLK_CTRL2
REFCLK_CTRL1
REFCLK
REFCLK_CTRL0
DAP_MCLK
OSC
SPDIF_MCLK
REFCLK
MUX_ MCLK
OSC
VCC
GND GND
VCC
GND GND GND
GND
U1
12.2880 MHZ
1
7 8
14
NC
GND CLKOUT
+5V
C1
47nf
C2
47nf
C3
47nf
C4
47nf
R3
0
U2C
74AC125SC
9 8
10
R4
33
U2A
74AC125SC
2 3
1
U2D
74AC125SC
1211
13
R106
75
R1
33
JP1
HDR3X1
1
2
3
TP2
R2
33
TP1
JP2
HEADER 3X2
12
34
56
U2B
74AC125SC
5 6
4
SPDIF_MCLK
REFCLK
REFCLK_CTRL[3..0]
DAP_MCLK
Figure 15. Master Clock Circuit
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