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CDB4228A

6 DS511DB1

7.1 Serial Mode

The SMODE[4..0] switches on S5 set the serial

mode and the LRCLK/SCLK direction of all other

devices in the system except the CS4228A. The de-

vices controlled by SMODE include the CS8414,

the CS8404, and the DAP. SMODE settings on S5

are only active when in EXTRNL mode. The

SMODE mapping is shown in Table 1. Care must

be taken when setting up SMODE so that the LR-

CLK/SCLK direction corresponds with the

CS4228A master/slave setting to avoid bus conten-

tion. The CS4228A serial port master/slave mode is

set in the Serial Port Mode register 0x0D.

7.2 MCLK Multiplexer

The board level MCLK source is controlled by the

MCLK-SEL[2..0] switches on S5 when in EX-

TRNL mode. The multiplexer settings are shown in

Table 3. The MCLK source should be the CS8414

whenever the S/PDIF data source is used.

7.3 Transmitter Clock Divider

The TX_MCLK[1..0] switches on S5 control the

clock divider for the CS8404 S/PDIF transmitter

when in EXTRNL mode. The transmitter must be

supplied a 128 Fs MCLK which is sourced from the

CS4228A MCLK multiplexer. The clock divider

ratios are shown in Table 5.

8. POWER SUPPLY CIRCUITRY

Power is supplied to the evaluation board by four

binding posts (+5V, GND, +12V, -12V). The +5V

input supplies power to the analog and digital +5

Volt circuitry and to a 3.3V voltage regulator.

There is a power supply header for selecting either

5V or 3.3V supplies to the CS4228A VL pin. A

second header selects the interface voltage for the

programmable logic device that supplies the con-

trol port interface. The VL setting should always be

equal or greater than the PLD PWR to prevent

noise due to charge injection.

9. GROUNDING AND POWER SUPPLY

DECOUPLING

The CS4228A requires careful attention to power

supply and grounding arrangements to optimize

performance. The decoupling capacitors are locat-

ed as close to the CS4228A as possible. Extensive

use of ground plane fill on both the analog and dig-

ital sections of the evaluation board yields large re-

ductions in radiated noise.

SMODE

[4..0]

Board Level Serial Mode CS8414

MODE

CS8404

MODE

DAP CLK

MODE

CS8414

M[3..0]

CS8404

M[2..0]

0 I2S, TX Master, 64Fs SCLK only Output Input Input 2 4

1 I2S, CODEC Master Input Input Input 3 4

2 I2S, DAP Master Input Input Output 3 4

3 Right Justified, TX Master, 16 bits Output Input Input 5 5

4 Right Justified, CODEC master Input OFF Input 15 4

5 Right Justified, DAP master Input OFF Output 15 4

6 Left Justified, CODEC master Input OFF Input 15 1

7 Left Justified, DAP master Input OFF Output 15 1

8 Left Justified, test mode Output Input Input 0 1

9 Left Justified, test mode Input Output Input 1 0

10 - 31 I2S, CODEC master Input Input Input 3 4

Table 1. Board Level Serial Mode Settings

1 2 3 4 5 6 7 8 9 10 11 ... 35 36

Evaluation Board for CS4228A 1
CDB4228A 10

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